1. Field of the Invention
This invention relates to a non-volatile semiconductor memory device which consists of memory cell units, such as NAND cells, AND cells, DINOR cells, etc., each formed of a plurality of memory cells connected to each other.
2. Description of the Related Art
An electrically erasable programmable EEPROM is known as a conventional non-volatile semiconductor memory device. In particular, attention has been paid to a NAND-cell type EEPROM consisting of a plurality of EEPROMs connected in series, since it is suitable to high integration.
Each memory cell (i.e. EEPROM) included in the NAND-cell type EEPROM has a FETMOS structure wherein a floating gate (a charged layer) and a control gate are provided on a semiconductor substrate with an insulating film interposed therebetween. Each NAND cell is constituted by a plurality of memory cells connected in series to each other. Each adjacent pair of the memory cells commonly use a single source and a single drain. A memory cell array is constituted by a plurality of NAND cells constructed as above and arranged in the form of a matrix.
The drains of NAND cells arranged in columns in the memory cell array are each located at an end of a corresponding NAND cell, and are commonly connected to a corresponding bit line via a corresponding selective gate transistor. On the other hand, the sources of the NAND cells arranged in columns are each located at the other end of a corresponding NAND cell, and are commonly connected to a common source line. The control gate of each memory transistor is connected to a corresponding one of control gate (word) lines arranged in rows in the memory cell array. The gate electrode of each selective gate transistor is connected to a corresponding one of selective gate lines arranged in rows in the memory cell array.
FIG. 7 is a plan view, showing a basic structure of each NAND cell formed of EEPROMs, while FIGS. 8A and 8B are sectional views, showing the structure. FIG. 9 shows a circuit equivalent to the NAND cell shown in FIG. 7. In this example, the NAND cell is constituted by connecting, in series, four memory cells M1-M4, two selective MOS transistors S1 and S2, and its source and drain diffusion layers. A plurality of NAND cells constructed as above constitute a memory cell array.
The drain of the memory cell M1 is connected to a bit line BL via a selective line S1. The source of the memory cell M4 is connected to a source line via a selective transistor S2. The control gates 6.sub.1 -6.sub.4 (CG1-CG4) of the memory cells M1-M4 are connected to a word line WL which intersects the bit line BL. Although in this case, each NAND cell consists of four memory cells, it can be formed of a number 2.sup.n of memory cells.
The cell structure will be explained in more detail with reference to FIGS. 8A and 8B. An n-well 11 is formed on a p-type silicon substrate 10, and a p-well 12 is formed on the n-well 11. Memory cells are formed on the p-well 12, and a peripheral circuit is provided in a region of the p-well other than the region of the same in which the memory cells are provided. The region in which the NAND cell is formed is defined by an element-separating insulation film 13.
Each memory cell comprises a first gate insulation film 3.sub.1 consisting of a thermally oxidized film with a thickness of 5-20 nm formed on the p-well 12; a floating gate 4 (4.sub.1, 4.sub.2, 4.sub.3, 4.sub.4) consisting of a first polycrystal silicon film with a thickness of 50-400 nm formed on the first gate insulation film 3.sub.1 ; a second gate insulation film 5 consisting of a thermally oxidized film with a thickness of 15-40 nm formed on the floating gate 4; and a control gate 6 (6.sub.1, 6.sub.2, 6.sub.3, 6.sub.4) consisting of a second polycrystal silicon film with a thickness of 100-400 nm formed on the second gate insulation film 5. The control gates 6 are continuously arranged in one direction and serve as a single word line WL.
An n-type layer 9 which serves as a source/drain diffusion layer is commonly used by each adjacent pair of the memory cells. The drain of the NAND cell, which is located at an end thereof, is connected to a bit line 8 via the selective MOS transistor S1 formed of a gate electrode 4.sub.5. The source of the NAND cell, which is located at the other end thereof, is grounded via the selective transistor S2 formed of the gate electrode 4.sub.6.
The two selective transistors S1 and S2 are provided by respectively forming, on the p-well 12, selective gates 4 (4.sub.5, 4.sub.6) consisting of the first polycrystal silicon film, with a third gate insulation film 32 consisting of a thermal oxide film with a thickness of 25-40 nm interposed therebetween. On the selective gates 4 (4.sub.5, 4.sub.6), the lines 6 (6.sub.5, 6.sub.6) consisting of the second polycrystal silicon film are provided, with the second gate insulation film 5 interposed therebetween. The selective gates 4.sub.5 and 4.sub.6 are connected to the lines 6.sub.5, 6.sub.6, respectively, via through holes (not shown) formed at regular intervals, thereby reducing the resistance of each line.
The floating gates 4.sub.1 -4.sub.4, the control gates 6.sub.1 -6.sub.4, the selective gates 4.sub.5 and 4.sub.6, and the lines 6.sub.5 and 6.sub.6 formed on the selective gates of all memory cells are simultaneously patterned using a single etching mask in the direction of channel length, thereby aligning the edges of the memory cells. The n-type layer 9 which serves as the source/drain diffusion layer is formed by injecting arsenic or phosphorus ions using, as masks, the control gates 6.sub.1 -6.sub.4 and the wires 6.sub.5 and 6.sub.6 on the selective gates.
In the above-described structure, the coupling capacity C.sub.1 between the floating gate 4 of each memory cell and the substrate 10 is set smaller than the coupling capacity C.sub.2 between the floating gate 4 and the control gate 6 of each memory cell. This will be explained using specific cell parameters. In accordance with the rule of a pattern size of 0.6 .mu.m, the floating gate and the control gate each have a width of 0.6 .mu.m, and those opposite end portions of each floating gate 4 which have a length of 0.6 .mu.m are provided on each adjacent pair of element-separating insulation films 13. Further, the first gate insulation film 3.sub.1 is formed of a thermal oxide film with a thickness of e.g. 10 nm, and the second insulation film 5 is formed of a thermal oxide film with a thickness of e.g. 28 nm. In this case, the following equations are established: EQU C.sub.1 =.epsilon./0.01 EQU C.sub.2 =3.epsilon./0.028
where .epsilon. represents the dielectric constant of each thermal oxide film.
Accordingly, C.sub.1 is smaller than C.sub.2.
FIG. 10 shows a circuit using a NAND cell. The following table 1 shows the relationship between the potentials of the gates, for explaining the erase, write and read operations of the circuit shown in FIG. 10.
TABLE 1 FLASH SELECTIVE WRITE READ ERASE (M.sub.4) (M.sub.4) BL1 V.sub.PP ' 0V 1-5V BL2 V.sub.PP ' V.sub.CC 0V SOURCE V.sub.PP ' 0V 0V SG1 V.sub.PP ' V.sub.CC V.sub.CC SG2 V.sub.PP ' 0V V.sub.CC CG1 0V 1/2 V.sub.PP V.sub.CC CG2 0V 1/2 V.sub.PP V.sub.CC CG3 0V 1/2 V.sub.PP V.sub.CC CG4 0V V.sub.PP 0V P WELL V.sub.PP ' 0V 0V N WELL V.sub.PP ' 0V 0V
First, an explanation will be given of flash erasion of data stored in all memory cells of the NAND cell ("flash erasion" means to erase all data at a time). In this example, the control gates CG1-CG4 of all memory cells of each NAND cell are set at 0 V, the gates SG1 and SG2 of the selective MOS transistors S11 and S21, the n-well 11 and the p-well 12 which surrounds the memory cells at "H" level (e.g. at a booster voltage Vpp1=18 V), and the bit lines BL1 and BL2 at Vpp1, too. As a result, an electric field occurs between the control gates of all memory cells and the p-well 12, and electrons flow from the floating gates 4 of the memory cells to the p-well 12 because of a tunnel effect. The erase operation shifts the threshold voltage of all memory cells M1-M4 to a negative value (-1--5 V). This state will be called a data "1" state (resulting from flash erasion).
An explanation will be given of writing data into the NAND cell. To write data into only the memory cell M4 located on the side of the bit line BL1, the gate SG1 of the selective transistor S11 on the side of the bit line BL1 is set to Vcc (e.g. 5 V), the gate SG2 of the selective transistor S21 on the side of the source line to 0 V, the control gate CG4 to "H" level (e.g. a booster voltage Vpp=12-20 V), and the other control gates CG1-CG3 to an intermediate voltage (e.g. 1/2 Vpp) between 0 V and the "H" level.
At this time, the bit line BL1 is set to 0 V, and the bit line BL2 to Vcc (e.g. 5 V). In this state, a high electric field is generated between the control gate of the memory cell M1, the n-type diffusion layer 9, and the p-well 12, and hence electrons flow from the p-well 12 and the n-type diffusion layer 9 to the floating gate of the memory cell M1 because of a tunnel effect. As a result, the memory cell M1 is shifted to a data "0" state, wherein the threshold voltage thereof is shifted to a positive value higher than 0 V. At this time, as regards non-selected memory cells (M5-M8), the channel voltage increases from Vcc-Vth (Vth represents the threshold voltage of the selective transistor S12) to about 1/2 Vpp as a result of capacitive coupling, when the control gates CG1-CG3 have increased from 0 V to 1/2 Vpp and the control gate CG4 has increased from 0 V to Vpp. At this time, the selective transistor S12 is cut off, and the channel of each non-selected memory cell is in a floating state. Accordingly, the threshold voltage of each non-selected memory cell is kept unchanged.
As regards the memory cells M1-M3 on the side of the bit line BL1, the control gate of each of them is set at Vpp/2, and the n-type diffusion layer 9 at 0 V. Therefore, these memory cells are in the write mode. However, the electric field therebetween is not strong, and accordingly no electrons flow into the floating gates of the memory cells M1-M3. Thus, these memory cells have their threshold voltage kept unchanged, and hence are kept in the data "1" state. Moreover, on the side of the non-selected bit line BL2, the control gates CG1-CG3 of the memory cells M5-M7 are set at the intermediate voltage Vpp/2, and the source, drain and channel of each of the memory cells are substantially set at Vpp/2. Accordingly, almost no electric field occurs between the floating gates of the memory cells and the diffusion layer 9, and no electrons flow into or from the floating gates. Thus, the threshold of the memory cells is kept unchanged, and the memory cells are kept in the data "1" state. In addition, since the memory cell M8 connected to the bit line BL2 has its control gate CG4 set at the "H" level (Vpp), and the source, drain and channel thereof are substantially set at Vpp/2, the memory cell M8 is in the write mode. Since, however, the electric field generated at the memory cell M8 is not strong, no electrons flow into its floating gate, with the result that its threshold voltage is kept unchanged and the memory cell is in the data "1" state.
As explained above, data is written into the memory cell M4 only.
An explanation will then be given of the case where data is written into the memory cell M3 of the NAND cell located next to the memory cell M4. In this case, the control gate CG3 of the memory cell M3 is increased to the "H" level (Vpp), the control gates CG1, CG2 and CG4 of the memory cells M1, M2 and M4 are set to the intermediate voltage Vpp/2. Further, the bit line BL1 on the side of the selected memory cell M3 is set to 0 V, and the other bit line BL2 to Vcc (e.g. 5 V). The two selective gates S11 and S12 have their gate voltages set to values identical to those employed in the case of writing data into the memory cell M4. As a result, data can be written into the memory cell M3. Similarly, data are sequentially written into the memory cells M2 and M1.
Although in the above-described writing, the "H" level (Vpp) voltage or the intermediate level (Vpp/2) voltage is applied to the control gate of each memory cell, the current which flows from each control gate (at the "H" level or the intermediate level) is of 10 .mu.A or less, since the current is the sum of a tunnel current and a junction leak current between the diffusion layer 9 and the p-well 12. Moreover, although at the time of flash erasion, the n-well 11 and the p-well 12 which surrounds the memory cells is increased to the "H" (Vpp1) level, the current which flows from the control gate at the "H" level is of 10 .mu.A or less, since the current is the sum of the tunnel current and a junction leak current between the n-well 11 and the p-type substrate 10.
Thus, a high voltage applied at the time of write and erase operations can be created by the booster circuit using even a low voltage of about 5 V applied from the outside to the IC. Further, since only a small amount of current flows, during writing, from the control gate at the high level, data can be written, at a time, into all memory cells connected to a single control gate. In other words, write can be performed in a "page mode", which contributes to high-speed write.
In addition, since in the above-described write and erase operations, no surface breakage occurs between the drain portion of each memory cell and the p-well while the tunnel current flows, the number of occasions where data can be rewritten can be increased, and the reliability of data storage can be enhanced. Also, since only a low voltage of about Vcc (e.g. 5 V) is applied to the gate electrode GS of each selective gate and to the non-selected bit line, separation of elements can easily be performed, and the element separation width can be set to a low value substantially equal to that employed in the conventional hot electron injection type EEPROM.
The manner of reading data, for example, from the memory cell M4 will now be explained. At the time of read, the power voltage Vcc (5 V) is applied to the two selective transistors SG1 and SG2 to turn them on. An "H" level (e.g. 5 V) voltage which can turn on a memory cell in the data-written state is applied to the control gates CG1, CG2 and CG3 of the non-selected memory cells M1, M2 and M3. The control gate CG4 of the selected memory cell M4 is set to an "L" level voltage (e.g. 0 V).
The bit line BL1 is set to an "H" level voltage (about 1-5 V), while the source line is set to 0 V. On the basis of whether or not a current flows through the bit line BL1, it is determined whether data read from the memory cell M4 is "1" or "0".
The above-described conventional NAND-cell type EEPROM has a block erase function for erasing only data stored in a selected block, and also a multi-block erase function for erasing only data stored in at least two selected blocks, as well as the chip erase function for flash-erasing data stored in all memory cells at a time.
FIG. 11 is a view, useful in explaining block erasion or multi-block erasion. Table 2 shows the relationship in potential between gates.
TABLE 2 BLOCK ERASE BLO V.sub.PP . . . . . . BL2047 V.sub.PP Cell-Source V.sub.PP SGD V.sub.SS FLOATING CG0 V.sub.SS (0V) CG1 V.sub.SS (0V) CG2 V.sub.SS (0V) CG3 V.sub.SS (0V) SGS V.sub.SS FLOATING TGi V.sub.SS (5V) TGj V.sub.CC (0V) P WELL V.sub.PP N WELL V.sub.PP P-TYPE SUBSTRATE V.sub.Ss (0V)
Specifically, FIG. 11 shows an i-th block BLKi to be erased (selected) and a j-th block BLKj not to be erased (non-selected). To perform the erase operation, common gate lines CG0-CG3 are set to Vss (0 V), and common gate lines SGD and SGS are set in a "Vss (=0 V) floating" state (in this state, the selective gate lines are first set to Vss and then shifted to a potential floating state). If the transfer gate signal TGi of the selected block BLKi is set to Vcc (5 V), transistors T1i-T6i become conductive, and control gates CG0i-CG3i are set to Vss (0 V). Thus, if the p-well and n-well in the memory cell section are set to a high voltage Vpp, data stored in the memory cells of the selected block BLKi are erased, and the memory cells are shifted to the data "1" state.
On the other hand, since the transfer gate signal TGj of the non-selected block BLKj is set at Vss (0 V), the transfer gate transistors T1j-T6j are in a non-conductive state, control gates CG0j-CG3j and selective gates SGDj and SGSj are in a floating state. Accordingly, the p-well and n-well in the memory section are set to the high voltage Vpp, the control gates CG0j-CG3j and selective gates SGDj and SGSj increase to a value substantially equal to Vpp as a result of capacitive coupling with the p-well. Accordingly, the electric field between the p-well and the floating gate of each memory cell in the non-selected block BLKj is not strong, and hence data stored therein is not erased.
The above-described conventional block erase operation has the following two problems:
The first problem lies in the potentials of the selective gates SGDi and SGSi in the selected block. If the p-well in the memory cell section is set to the high voltage Vpp at the time of block erasion, the potentials of the selective gates SGDi and SGSi of the selected block BLKi and those of the selective gates SGDj and SGSj of the non-selected block BLKj will increase as a result of capacitive coupling with the p-well. Since the transfer gate signal TGi of the selected block is Vcc (5 V) and the transfer gate transistors T1i-T6i are in a conductive state, the charges of the control gates SGDi and SGSi will flow, via the transistors T1i-T6i, to the common gate lines SGD and SGS which are in a floating state.
For example, in the case of a 16-Mbit NAND-cell type EEPROM, the capacitance of the common gate line SGD or SGS is estimated to be 7.1 PF, and the capacitance of the selective gate SGDi or SGSi is 2 PF. The potential of the selective gate SGDi or SGSi is 4.4 V under the conditions that the erase voltage Vpp is 20 V, and the threshold voltage is 0.43 V when the substrate bias of the transistor T1i or T6i is -Vcc (-5 V). Since in the case of 16 Mbits, the oxide film of the selective gate is 320 angstrom, the electric field applied to the oxide film is 4.9 MV/cm. Further, since in the case of 16 Mbits, the oxide film of the selective gate has a relatively great thickness of 320 angstrom, no problem will occur. However, in accordance with an increase in memory capacity, the oxide film of the selective gate becomes thinner. In the case, for example, of 32 Mbits, the thickness is 180 angstrom, and will be 90 angstrom in the case of 64 Mbits. Accordingly, an electric field of 10 MV/cm or more may be applied to the oxide film as the memory capacity increases, with the result that the oxide film may be seriously damaged.
The second problem lies in the transfer transistor. In light of that the fact that the high voltage Vpp is applied to the control gate of each memory cell at the time of writing data therein, the transfer transistor is set to have a low threshold voltage and a small substrate bias effect as aforementioned. For example, the transfer transistor is designed such that its threshold voltage is set to +0.21 V, +0.43 V, and +0.67 V when the substrate bias is 0 V, -5 V and -18 V, respectively. If the transistors T2j-T5j are not sufficiently cut off when the potential of the control gates CG0j-CG3j of the non-selected block BLKj increases, at the time of erasion, to Vpp as a result of capacitive coupling with the p-well, a large leak current flows through the common gate lines CG0-CG3 via the transistors T2j-T5j. Accordingly, the potential of the control gates CG0j-CG3j decreases, and data in the non-selected block BLKj are erroneously erased. Furthermore, the potential of the selective gates SGDj and SGSj decreases due to current leakage at the transistors T1j and T6j, thereby seriously damaging the oxide film of each selective gate transistor.
As explained above, since in the conventional NAND-cell type EEPROM, the potential of the selective gate line is set in a "Vss (=0 V) floating" state at the time of performing erasion in units of a block, the potential of the selective gate of a block, from which data are to be erased, is reduced, and a high voltage is applied to the oxide film of the selective gate, thereby seriously damaging the selective gate.
Further, so as to transmit a high voltage to the control gate at the time of writing, the transfer transistor has a low threshold voltage and a low substrate bias effect. Therefore, when a great amount of channel leak occurs at a transfer transistor in a non-selected block, erroneous erasion of memory cell data or breakage of the oxide film of a selective gate may well occur.